1. Field of the Art
This invention relates to a method and an apparatus for testing electrical properties of IC devices, particularly suitable for use in testing packaged IC devices such as, for example, EEPROM (Electrically Erasable Programmable ROM) and the like.
2. Prior Art
Generally, apparatus which are in use for testing electrical properties of packaged IC devices are largely constituted by an IC tester and an IC handler. An IC tester is arranged to check for defects of IC devices by measuring electrical properties of connected IC devices according to predetermined test patterns. On the other hand, an IC handler is arranged to electrically connect respective IC devices to the IC tester, and to classify tested IC devices according to test results.
Accordingly, the IC handler which is generally employed for connecting and disconnecting IC devices to and from the IC the IC tester is largely constituted by a test board for removably mounting IC devices thereon, a loader for feeding IC devices to the test board, an unloader for sorting out tested IC devices according to test results, and a transfer means for transferring IC devices from the loader to the test board and then from the test board to the unloader.
Normally, an IC device testing apparatus is arranged to test a plural number of IC devices simultaneously. Therefore, the test board is usually provided with a large number of contact portions, for example, 32, 64 or 128 contact portions which are arranged in arrayed in a matrix-like fashion. A large number of IC devices are set on the contact portions of a test board by a transfer means and set on an IC tester to test electrical properties of individual IC devices simultaneously.
For instance, in handling IC devices, it is the usual practice to use, as a container jig, a tray which is arranged to hold a large number of IC devices. A number of such trays are stacked on the loader, and IC devices are picked up therefrom one after another by the transfer means. Tested IC devices are sent to the unloader. At the unloader, IC devices are sorted according to test results, for example, into a qualified group and a disqualified group. As for an IC device container jig for use at the unloader, it is also the usual practice to employ trays which are similar in construction to the trays which are used at the loader. Further, generally the IC transfer means is constituted by a robot which is provided with suction gripper means for gripping package portions of IC devices. Furthermore, normally the IC loader and unloader are located in positions distant from a testing station. Therefore, IC devices need to be transferred from the loader to the test position and then from the test position to the unloader. For this purpose, an IC transfer means is provided between the loader and the test position and also between the test position and the unloader. For transfer of IC devices, the above-mentioned trays or other transfer jigs can be used as carriers. Alternatively, a test board can be used as a carrier fro IC devices if desired.
IC devices are tested not only under normal temperature conditions but also heated and cooled temperature conditions. For this purpose, IC devices are put in a constant temperature oven or a thermostatic chamber which can create predetermined temperature conditions, and a testing head of the tester is located within the thermostatic chamber. Prior to a test, IC devices are preheated within the thermostatic chamber. More particularly, IC devices are left in a thermostatic chamber for a predetermined time period to heat or cool them to a specified temperature before connection to a testing head.
Accordingly, in a case where a test board is used as a transfer jig, it has been the general practice to transfer the test board from the loader to the unloader through the thermostatic chamber and then return it to the loader, moving the test board cyclically to and from the loader and unloader. While being transferred on the test board, IC devices are heated or cooled to a predetermined temperature before the test board is disconnectibly connected to an interface board which is connected to the IC tester.
By the using an apparatus which is arranged as described above, a large number of IC devices can be tested simultaneously in an efficient manner. In addition, concurrently with a test on a number of IC devices, other succeeding or preceding IC devices are transferred to or from another test board at the loader and unloader and preheated on the way to the IC tester. Thus, the apparatus is arranged to test a large number of IC devices in a short period of time, by handling a plural number of IC devices concurrently in the respective stages.
Regarding integrated circuit devices, there are in use a large variety of IC devices which differ from each other in function, and each one of such IC device needs to be tested for electrical properties. For example, in the case of DRAM (Dynamic Random Access Memory), IC devices are tested by relatively simple patterns, which take almost uniform time in testing electrical properties of each IC device. It follows that a large number of IC devices which are mounted on a test board can be tested simultaneously by the same test program.
However, depending upon the types of IC devices, the test time can differ from one IC device to another. For instance, in the case of EEPROM, it is necessary to carry out a two-stage test on each IC device using a different pattern in each stage, i.e., to carry out a data write-in test in a first stage and a data erasure test in a second stage. In such a case, however, you cannot be sure if you can succeed in a data write-in test by one write-in action. Normally, the write-in action has to be repeated for a plural number of times. Besides, even among IC devices of the same type, a data write-in action may have to be repeated for a different number of times until succeeding in writing data in memory cells at a plural number of addresses. In the data write-in test, an IC device is judged as xe2x80x9cqualifiedxe2x80x9d when a set of data is successfully written into all of necessary memory cells at each address for a required number of times. The same applies to the data erasure test. Namely, in the data erasure test, an IC device is judged as xe2x80x9cqualifiedxe2x80x9d when data in all of memory cells are erased within a required number of times.
As described above, when testing IC devices such as EEPROM or the like, the testing time can vary largely from one IC device to another. In some cases, as compared with a shortest testing time, it may take a several to ten and several times longer testing time in finishing a test on some IC devices. Accordingly, when testing a large number of IC devices simultaneously in the manner as in the above-described prior art, the time duration of each test cycle needs to be extended according to those IC devices which would require the longest testing time. As a consequence, the testing time could become extremely long, making it difficult to test a large number of IC devices in speedy and efficient manner. These irregularities in testing time among the respective test boards greatly affect the progress of operations in other stages, i.e., the operations in the IC device loading, unloading and preheating stages.
In view of the foregoing situations, it is an object of the present invention to provide a method and an apparatus which make it possible to test IC devices smoothly and in an extremely efficient manner despite differences in testing time between individual IC devices.
In order to achieve the above-stated objective, according to the present invention, there is provided an apparatus for successively testing electrical properties of a large number of packaged IC devices, basically including a test board provided at a testing station and provided with a plural number of contacting sockets for receiving therein a plural number of IC devices for connection to an IC tester separately and independently of each other, a loader located at a loading station and adapted to feed untested IC devices toward the test board, an unloader located at an unloading station and adapted to discharge tested IC devices from the test board at the testing station, and a device transfer mechanism movable across the testing station to transfer untested IC devices from the loader to the testing station and to transfer tested IC devices from; the testing station to the unloader, the apparatus comprising: a detection means adapted to detect completion of an IC test conducted on an IC device in each socket of the test board; a means for operating the device transfer means in such a way as to pick up a tested IC device from the socket and replace same by a fresh IC device yet to be tested; and a means for detecting placement of the fresh IC device in the socket of said test board.
According to the present invention, there is also provided a method for successively testing electrical properties of a large number of packaged IC devices, comprising the steps of: successively picking up untested IC devices fed from a loading station by means of a device transfer mechanism and thereby feeding said IC devices successively to a plural number of contacting sockets on a test board of a testing station for connection to an IC tester; conducting a test on each one of the IC devices in the contacting sockets in the testing station concurrently and independently of each other; detecting completion of a test at each socket separately; upon detecting completion of a test at a socket, replacing a tested IC device in that socket by an untested fresh IC device by means of the device transfer mechanism; and upon detecting placement of the fresh IC device in said socket, starting again a test at that socket.
The above and other objects, features and advantages of the present invention will become apparent from the following particular description, taken in conjunction with the accompanying drawings which show by way of example a preferred embodiment of the invention. Needless to say, the present invention should not be construed as being limited particular forms shown in the drawings.